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19-3680; Rev 1; 12/07
KIT ATION EVALU E AILABL AV
10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset
Features
Ideal for Serializing Cell Phone Camera Parallel Interface MAX9225 Serializes 8-Bit YUV, HSYNC, and VSYNC LCDS Rejects Common-Mode Noise Automatic Location of Word Boundary After Signal Interruption Power-Down Control Through the Serial Link Power-Down Supply Current 0.5A (max) for MAX9225 3.0A (max) for MAX9226 +2.375V to +3.465V Core Supply Voltage Parallel I/O Interfaces Directly to 1.8V to 3.3V Logic 15kV Human Body Model ESD Protection -40C to +85C Operating Temperature Range
General Description
The MAX9225/MAX9226 serializer/deserializer chipset reduces wiring by serializing 10 bits onto a single differential pair. Ten bits are serialized in each cycle of the parallel input clock resulting in a 100Mbps to 200Mbps net serial-data rate. The MAX9225 serializes the 8-bit YUV, HSYNC and VSYNC outputs from a camera mounted in the flip part of the phone, reducing wiring through the hinge to the baseband processor in the base of the phone. The 2-wire serial interface uses low-current differential signaling (LCDS) for low EMI, high common-mode noise immunity, and ground-shift tolerance. The MAX9225/MAX9226 automatically identify the word boundary in the serial data in case of signal interruption. The MAX9226 power-down is controlled by the MAX9225. The MAX9225/MAX9226 consume 3.5A or less in power-down mode. The MAX9225 serializer operates from a single +2.375V to +3.465V supply and accepts +1.71V to +3.465V inputs. The MAX9226 deserializer operates from a +2.375V to +3.465V core supply and has a separate output buffer supply (V DDO ), allowing +1.71V to +3.465V output high levels. The MAX9225/MAX9226 are specified over the -40C to +85C extended temperature range and are available in 16-pin TQFN (3mm x 3mm x 0.8mm) packages with an exposed paddle.
MAX9225/MAX9226
Ordering Information
PART MAX9225ETE MAX9226ETE TEMP RANGE PINPACKAGE PKG TOP CODE MARK
-40C to +85C 16 TQFN-EP* T1633-4 ADO -40C to +85C 16 TQFN-EP* T1633-4 ADX
MAX9225ETE+ -40C to +85C 16 TQFN-EP* T1633-4 ADO MAX9226ETE+ -40C to +85C 16 TQFN-EP* T1633-4 ADX
Applications
Cell Phone Cameras Digital Cameras
+Denotes lead-free package. *EP = Exposed paddle.
Pin Configurations appear at end of data sheet.
Typical Application Circuit
LCDS PARALLEL DATA IN INPUT LATCH
PARALLEL TO SERIAL
SERIAL TO PARALLEL
OUTPUT LATCH
PARALLEL DATA OUT
PIXEL CLOCK IN
TIMING AND CONTROL
POWER-DOWN CONTROL TIMING AND CONTROL
DLL
PIXEL CLOCK OUT
MAX9225
MAX9226
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset MAX9225/MAX9226
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.5V to +4.0V VDDO to GND.........................................................-0.5V to +4.0V Serial Interface (SDO+, SDO-, SDI+, SDI-) to GND .....................................................-0.5V to +4.0V Single-Ended Inputs (DIN_, PCLKIN, PWRDN) to GND ....................................-0.5V to (VDD + 0.5V) Single-Ended Outputs (DOUT_, PCLKOUT) to GND ..............................-0.5V to (VDDO + 0.5V) Continuous Power Dissipation (TA = +70C) 16-Pin TQFN (3mm x 3mm x 0.8mm) Multilayer PCB (derate 20.8mW/C above +70C).............................................................1667mW Single-Layer PCB (derate 15.6mW/C above +70C).............................................................1250mW Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C ESD Protection (Human Body Model) SDO+, SDO-, SDI+, SDI- to GND ...............................> 15kV All Other Pins to GND ...................................................> 2kV
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (MAX9225)
(VDD = +2.375V to +3.465V, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = +2.5V, TA = +25C.) (Notes 1, 2)
PARAMETER High-Level Input Voltage Low-Level Input Voltage Input Current LCDS OUTPUT (SDO+, SDO-) Differential Output Current Output Short-Circuit Current POWER SUPPLY PCLKIN = 10MHz, 100Mbps Supply Current IDD VDD = 2.5V PCLKIN = 20MHz, 200Mbps PCLKIN = 10MHz, 100Mbps PCLKIN = 20MHz, 200Mbps 4.7 6.2 4.7 6.2 8.2 mA 8.2 10.6 mA 10.6 0.5 A IODH IODL IOS High level Low level Shorted to 0V or VDD 575 200 643 229 880 300 880 A A SYMBOL VIH VIL VIN = 0V to VDD IIN -0.3V VIN < 0V VDD < VIN (VDD + 0.3V) CONDITIONS MIN 1.19 -0.3 -20 -100 TYP MAX VDD + 0.3 +0.3 +20 +100 A UNITS V V SINGLE-ENDED INPUTS (PCLKIN, DIN_, PWRDN)
Worst-Case Pattern Supply Current
IDDW
VDD = 2.5V, Figure 1 All inputs = low
Power-Down Supply Current
IDDZ
2
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10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset
DC ELECTRICAL CHARACTERISTICS (MAX9226)
(VDD = +2.375V to +3.465V, VDDO = +1.71V to +3.465V, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = VDDO = +2.5V, TA = +25C.) (Notes 1, 2)
PARAMETER High-Level Output Voltage Low-Level Output Voltage Output Short-Circuit Current LCDS INPUT (SDI+, SDI-) Differential Input-Current Threshold Common-Mode Input Current IID IIC IIC = 0A, VDD = 3.3V 5% IIC = 0A, VDD = 2.8V 5% Differential Input Impedance ZID IIC = 0A, VDD = 2.5V 5% IIC = 300A, VDD = 3.3V 5% IIC = 300A, VDD = 2.8V 5% Common-Mode Input Impedance Input Capacitance POWER SUPPLY VDD = VDDO = 2.5V (Note 4) PCLKOUT = 10MHz, 100Mbps PCLKOUT = 20MHz, 200Mbps PCLKOUT = 10MHz, 100Mbps PCLKOUT = 20MHz, 200Mbps -5 -0.2 8.4 9.1 9.7 11.6 0.3 12 mA 12 12 mA 13 3.0 +5 +0.2 A % V ZIC CIN IIC = 300A SDI+ or SDI- to ground -300 69 82 95 67 86 90 400 400 90 108 125 91 108 167 2 +300 114 137 161 117 141 375 pF A A SYMBOL VOH VOL IOS CONDITIONS VDDO = +2.375V to +3.465V, IOH = -1mA VDDO = +2.375V to +3.465V, IOL = 1mA Output shorted to ground VDDO = 2.375V VDDO = 3.135V VDDO = 3.465V -2 -9 -25 mA MIN 0.8 x VDDO 0.2 TYP MAX UNITS V V SINGLE-ENDED OUTPUTS (PCLKOUT, DOUT_)
MAX9225/MAX9226
Supply Current
ITOT
Worst-Case Pattern Supply Current Power-Down Supply Current Supply Difference GROUND POTENTIAL Ground Difference
ITOTW
CL = 5pF, VDD = VDDO = 2.5V, Figure 2 (Note 4) (Note 4)
ITOTZ VSD VGD
MAX9225 VDD to MAX9226 VDD MAX9225 to MAX9226 ground difference
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10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset MAX9225/MAX9226
AC ELECTRICAL CHARACTERISTICS (MAX9225)
(VDD = +2.375V to +3.465V, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = +2.5V, TA = +25C.) (Note 3)
PARAMETER Input Rise Time Input Fall Time PCLKIN Period High-Level Pulse Width Low-Level Pulse Width Setup Time Hold Time SYMBOL tR tF tP tPWH tPWL tS tH 50 0.3 x tP 0.3 x tP 3 1 CONDITIONS MIN TYP MAX 2 2 100 0.7 x tP 0.7 x tP UNITS ns ns ns ns ns ns ns PCLKIN INPUT REQUIREMENTS (Figure 3)
AC ELECTRICAL CHARACTERISTICS (MAX9226)
(VDD = VDDO = +2.375V to +3.465V, CL = 5pF, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = VDDO = +2.5V, TA = +25C.) (Notes 3, 5)
PARAMETER PCLKOUT Period High-Level Pulse Width Low-Level Pulse Width Data Valid Before PCLKOUT Data Valid After PCLKOUT SERIALIZER AND DESERIALIZER LINK tPU1 Power-Up Time tPU2 Power-Down Time tPWRDN From VDD = VDDO = 2.375V when supplies are ramping up From PWRDN low to high From PWRDN high to low 2.8 11,264 x tP 4096 x tP 10 SYMBOL tP tPWH tPWL tVB tVA Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 CONDITIONS MIN 50 0.4 x tP 0.4 x tP 5 5 TYP MAX 100 0.6 x tP 0.6 x tP UNITS ns ns ns ns ns
ns
s
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +85C. Note 3: Parameters are guaranteed by design and characterization and are not production tested. Limits are set at 6 sigma. Note 4: ITOT = IDD + IDDO. Note 5: CL includes probe and test jig capacitance.
4
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10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset MAX9225/MAX9226
Test Circuits/Timing Diagrams
ODD DIN_ EVEN DIN_ PCLKIN
ODD DOUT_ EVEN DOUT_ PCLKOUT
Figure 1. Serializer Worst-Case Switching Pattern
Figure 2. Deserializer Worst-Case Switching Pattern
tP tPWL VIH PCLKIN
tF
tPWH VIH VIH
VIL
VIL tR tS tH VIH VIL
DIN_ PWRDN
VIH VIL
VIH IS THE MINIMUM HIGH-LEVEL INPUT, AND VIL IS THE MAXIMUM LOW-LEVEL INPUT (SEE THE DC ELECTRICAL CHARACTERISTICS TABLE)
Figure 3. Serializer Input Timing
tP tPWL VOH PCLKOUT VOL VOL VOH tPWH VOH
tVB DOUT_ VOH VOL
tVA VOH VOL
VOH IS THE MINIMUM HIGH-LEVEL OUTPUT, AND VOL IS THE MAXIMUM LOW-LEVEL OUTPUT (SEE THE DC ELECTRICAL CHARACTERISTICS TABLE)
Figure 4. Deserializer Output Timing
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10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset MAX9225/MAX9226
Typical Operating Characteristics
(VDD = VDDO = +2.8V, logic input levels = 0 to +2.8V, logic output load CL = 5pF, TA = +25C, unless otherwise noted.)
MAX9225 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9225 toc01
MAX9225 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9225 toc02
MAX9225 SUPPLY CURRENT vs. SUPPLY VOLTAGE
DIN[9:0] = WORST-CASE SWITCHING PATTERN PCLKIN = 20MHz
MAX9225 toc03 MAX9226 toc09 MAX9225 toc06
10
DIN[9:0] = ALL LOW PCLKIN = 20MHz
10
DIN[9:0] = ALL HIGH
10
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
PCLKIN = 20MHz
SUPPLY CURRENT (mA)
8
8
8
6 PCLKIN = 10MHz 4
6
6
4
PCLKIN = 10MHz
4
PCLKIN = 10MHz
2 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V)
2 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V)
2 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V)
MAX9225 SUPPLY CURRENT vs. FREQUENCY
MAX9225 toc04
MAX9225 SUPPLY CURRENT vs. FREQUENCY
DIN[9:0] = ALL HIGH
MAX9225 toc05
MAX9225 SUPPLY CURRENT vs. FREQUENCY
10 DIN[9:0] = WORST-CASE SWITCHING PATTERN
10
DIN[9:0] = ALL LOW
10
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
VDD = 3.3V VDD = 2.8V
SUPPLY CURRENT (mA)
8
8 VDD = 3.3V 6 VDD = 2.8V VDD = 2.5V 4
8 VDD = 3.3V VDD = 2.8V 6 VDD = 2.5V 4
6 VDD = 2.5V 4
2 10 12 14 16 18 20 FREQUENCY (MHz)
2 10 12 14 16 18 20 FREQUENCY (MHz)
2 10 12 14 16 18 20 FREQUENCY (MHz)
MAX9225 POWER-DOWN SUPPLY CURRENT vs. FREQUENCY
MAX9225 toc07
MAX9226 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9226 toc08
MAX9226 SUPPLY CURRENT vs. SUPPLY VOLTAGE
11 DIN[9:0] = ALL HIGH
0.20
0.16 SUPPLY CURRENT (A)
PCLKIN = LOW PWRDN = LOW DIN[9:0] = ALL LOW
11
DIN[9:0] = ALL LOW
0.12
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
10
PCLKOUT = 20MHz
10
PCLKOUT = 20MHz
9
9
0.08
0.04
8
PCLKOUT = 10MHz
8
PCLKOUT = 10MHz
0 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (MHz)
7 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V)
7 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V)
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10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset
Typical Operating Characteristics (continued)
(VDD = VDDO = +2.8V, logic input levels = 0 to +2.8V, logic output load CL = 5pF, TA = +25C, unless otherwise noted.)
MAX9226 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9226 toc10
MAX9225/MAX9226
MAX9226 SUPPLY CURRENT vs. FREQUENCY
MAX9226 toc11
MAX9226 SUPPLY CURRENT vs. FREQUENCY
DIN[9:0] = ALL HIGH
MAX9226 toc12
11
DIN[9:0] = WORST-CASE SWITCHING PATTERN
11
DIN[9:0] = ALL LOW
11
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
VDD = 3.3V VDD = 2.8V 9 VDD = 2.5V 8
SUPPLY CURRENT (mA)
10
PCLKOUT = 20MHz
10
10 VDD = 3.3V 9 VDD = 2.8V
9
VDD = 2.5V 8
8
PCLKOUT = 10MHz
7 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V)
7 10 12 14 16 18 20 FREQUENCY (MHz)
7 10 12 14 16 18 20 FREQUENCY (MHz)
MAX9226 SUPPLY CURRENT vs. FREQUENCY
MAX9226 toc13
MAX9226 POWER-DOWN SUPPLY CURRENT vs. FREQUENCY
SDI+/SDI- PULLED UP TO VDD DOUT[9:0] = ALL LOW
MAX9226 toc14
MAX9226 DOUT OUTPUT-HIGH VOLTAGE vs. SOURCE CURRENT
MAX9226 toc15
11
DIN[9:0] = WORST-CASE SWITCHING PATTERN
0.6
2.75 2.50 VDDO = 2.375V 2.25 DOUT (V)
SUPPLY CURRENT (mA)
VDD = 3.3V 9 VDD = 2.8V
SUPPLY CURRENT (A)
10
0.5
0.4
2.00 1.75
VDDO = 2V
VDD = 2.5V 8
0.3 1.50
VDDO = 1.71V
7 10 12 14 16 18 20 FREQUENCY (MHz)
0.2 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V)
1.25 0 0.2 0.4 0.6 0.8 1.0 SOURCE CURRENT (mA)
MAX9226 DOUT OUTPUT-LOW VOLTAGE vs. SINK CURRENT
MAX9226 toc16
MAX9226 DIFFERENTIAL INPUT IMPEDANCE vs. SUPPLY VOLTAGE
MAX9226 toc17
150
VDDO = +1.71V TO +2.375V
160
120
90
INPUT IMPEDANCE () 0 1.0
140
DOUT (mV)
120
60
30
100
0 0.2 0.4 0.6 0.8 SINK CURRENT (mA)
80 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V)
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10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset MAX9225/MAX9226
Pin Description (MAX9225)
PIN 1-7, 14, 15, 16 8 9 10 11 12 13 -- NAME FUNCTION DIN6-DIN0, Single-Ended Parallel Data Inputs. The 10 data bits are loaded into the input latch on the rising DIN9, DIN8, DIN7 edge of PCLKIN. 1.71V to 3.465V tolerant. Internally pulled down to GND. PCLKIN PWRDN SDOSDO+ GND VDD EP Parallel Clock Input. The rising edge of PCLKIN (typically the pixel clock) latches the parallel data input. Internally pulled down to GND. Power-Down Input. Pull PWRDN low to place the MAX9225/MAX9226 in power-down mode. Drive PWRDN high for normal operation. Internally pulled down to GND. Inverting LCDS Serial-Data Output Noninverting LCDS Serial-Data Output Ground Core Supply Voltage. Bypass to GND with 0.1F and 0.01F capacitors in parallel as close to the device as possible with the smallest value capacitor closest to the supply pin. Exposed Paddle. Connect EP to ground.
Pin Description (MAX9226)
PIN 1 2 3 4 5 6-15 16 -- NAME GND SDI+ SDIVDD PCLKOUT DOUT0-DOUT9 VDDO EP Ground Noninverting LCDS Serial-Data Input Inverting LCDS Serial-Data Input Core Supply Voltage. Bypass to GND with 0.1F and 0.01F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. Parallel Clock Output. Parallel output data are valid on the rising edge of PCLKOUT (typically the pixel clock). Single-Ended Parallel Data Output. DOUT[9:0] are valid on the rising edge of PCLKOUT. Output Supply Voltage. Bypass to GND with 0.1F and 0.01F capacitors in parallel as close to the device as possible with the smallest value capacitor closest to the supply pin. Exposed Paddle. Connect EP to ground. FUNCTION
8
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10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset
Functional Diagram (MAX9225) Functional Diagram (MAX9226)
MAX9225/MAX9226
SDO+ INPUT LATCH
SDI+ SDI-
DIN[9:0]
PARALLEL TO SERIAL
SDO-
SERIAL TO PARALLEL
OUTPUT LATCH
DOUT[9:0]
PCLKIN
TIMING AND CONTROL PWRDN TIMING AND CONTROL DLL PCLKOUT
MAX9225
MAX9226
Detailed Description
The MAX9225 serializer operates at a 10MHz-to-20MHz parallel clock frequency, serializing 10 bits of parallel input data DIN[9:0] in each cycle of the parallel clock. DIN[9:0] are latched on the rising edge of PCLKIN. The data and internally generated serial clock are combined and transmitted through SDO+/SDO- using multilevel LCDS. The MAX9226 deserializer receives the LCDS signal on SDI+/SDI-. The deserialized data and recovered parallel clock are available at DOUT[9:0] and PCLKOUT. Output data is valid on the rising edge of PCLKOUT. Bit 0 (DIN[0]) is transmitted first. Boundary bits OH1 and OH2 are used by the MAX9226 deserializer to identify the word boundary. OH1 is the inverse polarity of data bit 9 (DIN[9]), and OH2 is the inverse polarity of OH1. Therefore, at least two level transitions are guaranteed in one word. The clock is recovered from the serial input. Serial word format:
0 1 2 3 4 5 6 7 8 9 OH1 OH2
LCDS
The MAX9225/MAX9226 use a proprietary multilevel LCDS interface. Figure 5 provides a representation of the data and clock in the multilevel LCDS interface. This interface offers advantages over other chipsets, such as requiring only one differential pair as the transmission medium, the inherently aligned data and clock, and much smaller current levels than the 4mA typically found in traditional LVDS interfaces.
MAX9225/MAX9226 Handshaking
The handshaking function of the MAX9225/MAX9226 provides bidirectional communication between the two devices in case a word boundary error is detected. Prior to data transmission, the MAX9225 serializer adds boundary bits (OH) to the end of the latched word. These boundary bits are the inverse of the last bit of the latched word. During data transmission, the MAX9226 deserializer continuously monitors the state of the boundary bits of each word. If a word boundary error is detected, the serial link is pulled up to VDD and the MAX9226 powers down. The MAX9225 detects the pullup of the serial link and powers down for 1.0s. After 1.0s, the MAX9225 powers up, causing the power-up of the MAX9226. Then the word boundary is reestablished, and data transfer resumes. The handshaking function is disabled when PWRDN is pulled low.
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10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset MAX9225/MAX9226
PARALLEL DATA INPUT
PCLK IN
DIN[9:0]
DIN EXAMPLE INPUT
0 1
1 1
2 0
3 1
4 0
5 0
6 1
7 0
8 1
9 1
LCDS SERIAL-DATA OUTPUT FOR EXAMPLE INPUT (SD0+/SDO-)
1
1
0
1
0
0
1
0
1
1
OH1
OH2
NOTE: OH1 AND OH2 ARE OPPOSITE POLARITY.
Figure 5. Multilevel LCDS Output Representation
Applications Information
PCLKIN Latch Edge
The parallel data input of the MAX9225 serializer is latched on the rising edge of PCLKIN. Figure 3 shows the serializer input timing.
PCLKOUT Strobe
The serial-data output of the MAX9226 deserializer is valid on the rising edge of PCLKOUT. Figure 4 shows the deserializer output timing.
LCDS output is not driven until the DLL locks. 11,264 clock cycles are required for the power-up and link synchronization before valid DIN can be latched. See Figure 6 for an overall power-up and power-down timing diagram. For normal operation, PCLKIN must be running and settled before driving PWRDN high. If VDD = 0, the LCDS outputs are high impedance to ground and differential.
Ground-Shift Tolerance
The MAX9225/MAX9226 are designed to function normally in the event of a slight shift in ground potential. However, the MAX9226 deserializer ground must be within 0.2V relative to the MAX9225 serializer ground to maintain proper operation.
Power-Down and Power-Up
Driving PWRDN low puts the MAX9225 in power-down mode and sends a pulse to power down the MAX9226. In power-down mode, the DLL is stopped, SDO+/SDOare high impedance to ground and differential, and the LCDS link is weakly biased around (VDD - 0.8V). With PWRDN and all inputs low, the combined MAX9225/ MAX9226 supply current is reduced to 3.5A or less. Driving PWRDN high starts DLL lock to PCLKIN and initiates a MAX9226 power-up sequence. The MAX9225
MAX9226 Output Buffer Supply (VDDO) The MAX9226 parallel outputs are powered from VDDO, which accepts a +1.71V to +3.465V supply, allowing direct interface to inputs with 1.8V to 3.3V logic levels.
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10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset MAX9225/MAX9226
IN POWERDOWN POWER-UP AND LINK SYNCHRONIZATION DATA TRANSFER POWERDOWN tPWRDN PWRDN IN POWERDOWN
1 PCLKIN
2
tPU2
DIN_
DON'T CARE
1
N
DON'T CARE
LOW DOUT_
1
N
LOW
PCLKOUT
HIGH
HIGH
Figure 6. MAX9225/MAX9226 Power-Up/Power-Down Sequence
Flex Cable, PCB Interconnect, and Connectors
Interconnect for LCDS typically has a differential impedance of 100. Use interconnect and connectors that have matched differential impedance to minimize impedance discontinuities.
1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF
RD 1.5k DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
Board Layout and Supply Bypassing
Separate the LVTTL/LVCMOS and LCDS signals to prevent crosstalk. A PCB or flex with separate layers for power, ground, and signals is recommended. Bypass each VDD and VDDO pin with high-frequency, surface-mount ceramic 0.1F and 0.01F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin.
Figure 7. Human Body Model ESD Test Circuit
Chip Information
PROCESS: CMOS
ESD Protection
The MAX9225/MAX9226 are rated for 15kV ESD protection using the Human Body Model. The Human Body Model discharge components are CS = 100pF and RD = 1.5k (Figure 7).
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10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset MAX9225/MAX9226
Pin Configurations
PWRDN
TOP VIEW
SDO+ SDOGND
DOUT6
DOUT5
12 VDD 13 DIN9 14 DIN8 15 DIN7 16 1 DIN6
11
10
9 8 7 PCLKIN DIN0 DIN1 DIN2 DOUT7 13 DOUT8 14 DOUT9 15 VDDO 16
12
11
10
DOUT4
DOUT3 9 8 7 DOUT2 DOUT1 DOUT0 PCLKOUT 6 5 4 VDD
MAX9225
6 5
MAX9226
2 DIN5
3 DIN4
4 DIN3
1 GND
2 SDI+
3 SDI-
TQFN-EP
TQFN-EP
12
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10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
12x16L QFN THIN.EPS
MAX9225/MAX9226
MARKING
E E/2
(ND - 1) X e
(NE - 1) X e
D2/2
D/2 D
AAAA
C L
e D2
k
b E2/2
0.10 M C A B
C L
L
E2
0.10 C
0.08 C A A2 A1 L
C L
C L
L
e
e
PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x0.8mm
21-0136
I
1 2
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10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset MAX9225/MAX9226
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PKG REF. A b D E e L N ND NE A1 A2 k 0.25 0 0.35
8L 3x3 MIN. NOM. MAX. 0.70 0.25 2.90 2.90 0.75 0.30 3.00 3.00 0.55 8 2 2 0.02 0.20 REF 0.25 0.05 0 0.80 0.35 3.10 3.10 0.75
12L 3x3 MIN. NOM. MAX. 0.70 0.20 2.90 2.90 0.45 0.75 0.25 3.00 3.00 0.50 BSC. 0.55 12 3 3 0.02 0.20 REF 0.25 0.05 0 0.65 0.30 0.80 0.30 3.10 3.10
16L 3x3 MIN. NOM. MAX. 0.70 0.20 2.90 2.90 0.75 0.25 3.00 3.00 0.40 16 4 4 0.02 0.20 REF 0.05 0.80 0.30 3.10 3.10 0.50 PKG. CODES TQ833-1 T1233-1 T1233-3 T1233-4 T1633-2 T1633F-3 T1633FH-3 T1633-4 T1633-5
EXPOSED PAD VARIATIONS
D2 MIN. 0.25 0.95 0.95 0.95 0.95 0.65 0.65 0.95 0.95 NOM. 0.70 1.10 1.10 1.10 1.10 0.80 0.80 1.10 1.10 MAX. 1.25 1.25 1.25 1.25 1.25 0.95 0.95 1.25 1.25 MIN. 0.25 0.95 0.95 0.95 0.95 0.65 0.65 0.95 0.95 E2 NOM. 0.70 1.10 1.10 1.10 1.10 0.80 0.80 1.10 1.10 MAX. 1.25 1.25 1.25 1.25 1.25 0.95 0.95 1.25 1.25 PIN ID 0.35 x 45 0.35 x 45 0.35 x 45 0.35 x 45 0.35 x 45 0.225 x 45 0.225 x 45 0.35 x 45 0.35 x 45 JEDEC WEEC WEED-1 WEED-1 WEED-1 WEED-2 WEED-2 WEED-2 WEED-2 WEED-2
0.65 BSC.
0.50 BSC.
NOTES: 1. 2. 3. 4. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. N IS THE TOTAL NUMBER OF TERMINALS. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS . DRAWING CONFORMS TO JEDEC MO220 REVISION C. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY. WARPAGE NOT TO EXCEED 0.10mm.
5. 6. 7. 8. 9. 10. 11. 12.
PACKAGE OUTLINE 8, 12, 16L THIN QFN, 3x3x0.8mm
21-0136
I
2 2
14
______________________________________________________________________________________
10-Bit, Low-Power, 10MHz-to-20MHz Serializer and Deserializer Chipset MAX9225/MAX9226
Revision History
REVISION NUMBER 0 1 REVISION DATE 1/06 12/07 Initial release Changed max output short-circuit current from -20 to -25 in EC table; various style changes. DESCRIPTION PAGES CHANGED -- 2, 3, 11
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(c) 2007 Maxim Integrated Products
Springer
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